Current integration of magneto-resistive random access memory (“MRAM”) technology (based on toggle mode operation) requires precise control of dielectric planarity and a residue free surface to enable high fidelity magnetic performance across chip and across wafer. However, one such issue which has arisen when working towards achieving these requirements is that the fabrication of the via connecting the magnetics to the word line often results in significant amounts of residue which hinders device yield. The root cause of this problem has been traced to the chemical mechanical polishing steps of the Copper (“Cu) and tantalum (“Ta”) via plug material, which results in residual slurry particles. Current processes that try to overcome this problem are usually limited by the material being polished. Furthermore, when scaling to potential spin torque structures, this integration places a greater dependence on magnetic shape anisotropy from patterning as a full stack etch is performed (as compared to the conventional SOA approach used in Toggle mode operation).